// module name: tb_ram_rom
// author: yangtao2019
// date: 2021.07.11



module tb_ram_rom;

    reg[31:0]  data_in;
    reg clk;
    reg read, write;
    reg[6:0] rom_addr, ram_addr;

    wire[31:0] ram_data_out, rom_data_out;

    rom inst_rom0(.addr(rom_addr), .read_data(rom_data_out));
    ram data_ram0(.clk(clk), .read(read), .write(write), .addr(rom_addr), .read_data(ram_data_out), .write_data(data_in));

    initial begin
        clk = 0;
        read = 0;
        write = 0;
    end

    initial begin
        forever #20 clk = ~clk;
    end

    // ROM read test
    initial begin
        #50
        rom_addr = 7'd0;
        forever #50 rom_addr = rom_addr + 1'b1;
    end

    integer i;
    initial begin: RAMTEST
        // RAM read test
        #50
        ram_addr = 7'd0;
        read = 1'b1;
        write = 1'b0;
        data_in = 32'h0000_0000;
        for(i=0;i<7'h7f;i=i+1) begin
            #50
            ram_addr = ram_addr + 1'b1;
        end 

        // RAM write test
        #500
        ram_addr = 7'd0;
        read = 1'b0;
        write = 1'b1;
        data_in = 32'hffff_ffff;
        for(i=0;i<7'h7f;i=i+1) begin
            #70
            ram_addr = ram_addr + 1'b1;
        end

        // RAM read test
        #50
        ram_addr = 7'd0;
        read = 1'b1;
        write = 1'b0;
        data_in = 32'h0000_0000;
        for(i=0;i<7'h7f;i=i+1) begin
            #50
            ram_addr = ram_addr + 1'b1;
        end
    end

endmodule
